The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Nowadays, the semiconductor devices and integrated circuits include multi-layer structures having dimensions smaller than one micrometer. As known in the art, a photolithography process is a step that determines the critical dimension (CD) in the manufacture of a semiconductor integrated circuit device. Electric circuit patterns are formed by first transferring the pattern on a photo mask to a photoresist layer in a photolithography process, and then transferring the pattern from the photoresist layer to an underlying material layer such as a dielectric layer or a metal layer in a subsequent etching process.
In addition to the control of CD, a successful photolithography process on a wafer includes alignment accuracy (AA). As the scaling down continues especially below 20 nm, aligning multiple layers accurately has become more and more difficult. Therefore, the measurement of accuracy, i.e., the measurement of overlay error, is crucial to the semiconductor fabrication process. An overlay mark is used as a tool for measuring overlay error and to determine whether the photoresist pattern is precisely aligned with the previous layer on a wafer after a photolithography process.
If all or part of the mask is not aligned properly, the resulting features may not align correctly with adjoining layers. This may result in reduced device performance or complete device failure. While existing overlay marks have been used to prevent this, they have not been entirely satisfactory for small dimensional devices.